The present invention relates to a method for testing sub-system modules of a design for an integrated circuit, and more specifically for testing sub-system modules of a design for a network interface.
During the design and development of an integrated circuit, such as a network interface, the individual components of the integrated circuit can be tested and the integrated circuit itself can be tested after completion of the entire circuit. However, the components which make up sub-system modules of the integrated circuit cannot be tested until the entire integrated circuit has been constructed. Failure to test the individual sub-systems prior to completion of the entire integrated circuit causes undue delay and further complicates the final testing. For example, if the design and construction of one sub-system of the network interface is delayed, then the testing of the entire network interface is delayed.
In addition, identifying component specific problems can be difficult because problems can be compounded by various sub-system modules. The compounded problems can lead to misdiagnoses, as well as causing further delays.
There is a need for a method to test and verify sub-system modules which when combined to form a complete integrated circuit. There is also a need to be able to incorporate smaller sub-systems into larger sub-systems in order to test the larger sub-systems prior to completion of the integrated circuit. There is also a need to be able to test and verify an integrated circuit in a more efficient manner.
These and other needs are attained by the present invention, where a design for an integrated circuit is defined into sub-system modules and the sub-system modules are tested and verified using system parameters for the integrated circuit. The sub-system modules can be tested individually, in combination with other sub-system modules and as a completed integrated circuit. Each of the sub-system modules can be tested using system tasks. For example, sub-system module containing memory can have data written into the memory and read from the memory to verify that the memory is functioning properly. After a sub-system module passes a verification test, a single or plurality of sub-system modules can be combined with the sub-system module to form a larger sub-system module.
Testing and verifying the sub-system modules in a progressive manner provides an efficient verification of the integrated circuit design. In addition, since problems can be identified easier, a design can be modified or re-designed to overcome a problem with a current design, if necessary.
Additional advantages and novel features of the invention will be set forth in part in the description which follows, and in part will become apparent to those skilled in the art upon examination of the following or may be learned by practice of the invention. The advantages of the invention may be realized and attained by means of the instrumentalities and combinations particularly pointed out in the appended claims.